PyTorch Conference Europe 2026, 8 April 2026
De-mystifying PyTorch for ASICs
When, and why, to move your model development onto AI accelerators.
- Organizer
- Linux Foundation
- Venue
- Station F, Paris, France
- Attendees
- 100
- Type
- Talk
- Level
- Intermediate
- Duration
- 30 minutes
- PyTorch
- H100
- TPU
- Trainium
- ASICs
- Benchmarking
Abstract
How and why to move PyTorch development onto AI accelerators. Covers how ASICs and the XLA/Neuron compilers work, PyTorch/XLA on Google TPU and TorchNeuronX on AWS Trainium, the performance picture and the 'compiler tax', the common ASIC errors you'll hit, and a practical migration decision framework, benchmarked across H100, TPU v6e, and Trainium.
Outline
- Deep learning computations and how ASICs and XLA work
- Google TPU with PyTorch/XLA
- AWS Trainium with TorchNeuronX
- Performance analysis and the 'compiler tax'
- Common ASIC errors (device busy, OOM) and their fixes
- Migration decision notes: when to move
- The way forward: TorchTPU, MAIA 200, TPU v7 vs Trainium3 vs NVIDIA
Key takeaways
- PyTorch/XLA and TorchNeuronX let you keep PyTorch while targeting TPU and Trainium
- Budget for the 'compiler tax': graph compilation and torch_xla.sync() change how you code
- Most ASIC failures are device-busy or OOM, with known, quick fixes
- ASICs build on top of PyTorch, so your skills transfer